1. Field of the Invention
The present invention relates, in general, to the testing of integrated circuits (ICs) and, more specifically, to a method and circuit for testing integrated circuit (IC) output pin circuitry, and connections between pins of ICs on circuit boards.
2. Description of Related Art
A common way to provide test access to digital pin signals of an IC is to implement digital boundary scan according to the rules defined in the “IEEE Standard Test Access Port and Boundary-Scan Architecture”, published in 1990 and 2001, by the Institute for Electrical and Electronic Engineers (IEEE), which is also known as IEEE Std. 1149.1-2001, or simply 1149.1. A dominant characteristic of 1149.1 is the use of a test access port (TAP) controller that has a prescribed state diagram, an Instruction Register (IR), and multiple Data Registers (DR), one of which is the Boundary Scan Register (BSR). FIG. 5 is a state diagram which shows all possible states of an 1149.1 TAP controller.
Note that bond pads of a bare integrated circuit die are eventually connected to the pins of an encapsulating package. Accordingly, in the present disclosure, the terms “pin”, “bond pad” and “pad” will be used interchangeably.
Recently, 1149.1 has been shown to be suitable for facilitating reduced pin-count testing of high pin-count ICs, which can significantly reduce the cost of testing the ICs. To enable this method, pin circuitry is first made bidirectional by the provision of input buffers 11 and output drivers 15 connected to bond pad 17, as shown in FIG. 1, and then boundary scan circuitry is added, as shown in FIG. 2. The boundary scan circuitry includes a shift register element 19 for testing the enable input of output driver 15, and a shift register element 21 for testing the data input of driver 15. Register element 21 includes a storage register (not shown) for storing an output data value and/or a captured data value. Output driver 15 is enabled by an enable bit stored in register element 19. The output data value and/or captured data value is stored in the storage register in register element 21. To permit implementation of a HIGHZ instruction defined by 1149.1, a slight modification is needed for the BSR-controlled pad driver circuitry 30 of FIG. 3, to facilitate simultaneously tristating (disabling) all output drivers. The modification comprises an AND gate 23 which receives the output of register 19 and an inverted forceDisable (tristating) signal. Thus, when the forceDisable signal is inactive (logic 0), the state of the enable input of output driver 15 is determined by the output of register 19. An active forceDisable signal is applied to override the output of the shift register.
Applicant's U.S. patent application Ser. No. 09/570,412 filed May 12, 2000, for “Method and Circuit for Testing D.C. Parameters of Circuit Input and Output Nodes” (Applicant's Docket LVPAT017US), now U.S. Pat. No. 6,586,921 B1 granted on Jul. 1, 2003, incorporated herein by reference, discloses a method by which the simultaneous tristate function is tested for unconnected pins of an IC using the timing shown in FIG. 4. In that method, at time t1, the pins are tri-stated in response to an instruction being loaded into the IC. Subsequently, at time tD, the data input to the output drivers is changed. Then, at time t2, the logic value of the pad is captured. If the logic value changed in response to the data input change, then the tristate functionality is defective (for example, forceDisable is stuck at 0), and the chip fails the test. The sequence of states shown in FIG. 4 is in accordance with 1149.1. This test does not, however, test whether the Enable bit in the BSR is stuck on (due to a defect).
To test circuit boards that contain ICs constructed according to 1149.1, different patterns of output driver logic values are shifted into the ICs during the Shift-DR state (the state is re-entered once per bit until all boundary scan bits have been shifted into all ICs), and the resultant logic value on each I/O interconnect is captured during the Capture-DR state. Then, another set of values is shifted in during the next transit through the Shift-DR state.
One problem with this test approach is that the minimum duration of the logic value of each output pin during testing is limited by the time required to reload the boundary scan register. For example, if ten ICs, each with a 100 bit boundary scan chain, are connected in series, then the time to reload the scan chain is one thousand periods of the test clock TCK during the Shift-DR state of the TAP (see FIG. 5). If the clock period is the typical value of one microsecond, then the minimal time to reload the scan chain is one millisecond. Although this is a short time compared to total test time, any high powered pin drivers that are short-circuited for that duration of time may be damaged by the heat generated within its transistors while the abnormally high current is flowing. In some cases, damage can occur in tens of microseconds, and is sufficient to reduce the expected lifetime of the circuit.
Whetsel U.S. Pat. No. 5,706,296 granted on Jan. 6, 1998 for “Bi-directional Scan Design with Memory and Latching Circuitry” proposes a solution to this problem. The proposal includes providing a latching action in the output driver path so that a short circuit causes the driver to stop driving its intended logic value and switches to driving the opposite logic value. This approach requires modifying the driver's circuitry, to insert a delay in the output path, and may flip the driver's state if a very low impedance load is connected that is within specification.
Terayama U.S. Pat. No. 5,736,849 granted on Apr. 7, 1998 for “Semiconductor Device and Test Method for Connection Between Semiconductor Devices” proposes a solution which provides a weak output driver and a strong driver connected in parallel. During test mode, only the weak driver is enabled. As with the Whetsel solution, this circuit requires modification of the driver circuitry, and may not be able to drive a very low impedance load that is within specification.